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Optimizing for Best Power during Place & Route in Low Power SoC Designs
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"Optimizing for Best Power during Place & Route in Low Power SoC Designs"

Optimize power earlier in the flow and become more efficient during place-and-route

The integrated circuit (IC) design community commonly uses the phrase performance, power, and area (“PPA” for short) when describing the three key areas to focus on in optimizing an IC design.

Traditionally, when talking about PPA metrics, “performance” has been the primary focus. But as designs have moved to smaller, more advanced process nodes, power has at times pushed “performance” aside to become the dominant focus in PPA. Of course, designers don’t want slower-performing chips, but power consumption is growing in importance.

Many of the challenges of achieving low power during physical implementation relate to the kind of optimizations the software performs throughout the flow to achieve low power goals. Siemens Aprisa place-and-route tool addresses power challenges in two primary ways:

  • PowerFirst implementation technology to reduce total power consumption
  • Multi-domain methodology support


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